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W83628F & W83629D PCI TO ISA BRIDGE SET
Table of Content1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION .............................................................................................................. 3 FEATURES...................................................................................................................................... 3 PACKAGE........................................................................................................................................ 3 BLOCK DIAGRAM OF W83628F .................................................................................................... 4 BLOCK DIAGRAM OF W83629D.................................................................................................... 5 PIN CONFIGURATION.................................................................................................................... 6 6.1 6.2 7. 7.1 PIN CONFIGURATION FOR 628F........................................................................................ 6 PIN CONFIGURATION FOR 629D ....................................................................................... 7 W83628F PIN DESCRIPTION............................................................................................... 8
7.1.1 7.1.2 7.1.3 7.1.4 PCI Interface .......................................................................................................................... 8 Control Logic and Handshaking Signals ................................................................................. 9 ISA Interface Signals ............................................................................................................ 10 Power Signals....................................................................................................................... 11 Control Logic and Handshaking Signals ............................................................................... 12 PC/PCI Interface .................................................................................................................. 12 IRQ Serializer Interface ........................................................................................................ 13 Power Signals....................................................................................................................... 13 NC Pins ................................................................................................................................ 13
PIN DESCRIPTION ......................................................................................................................... 8
7.2
W83629D PIN DESCRIPTION ............................................................................................ 12
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5
8.
PCI CONFIGURATION REGISTERS............................................................................................ 14 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 VID-VENDOR IDENTIFICATION REGISTER ..................................................................... 14 DID-DEVICE IDENTIFICATION REGISTER....................................................................... 14 PCICMD-PCI COMMAND REGISTER................................................................................ 14 PCISTS-PCI STATUS REGISTER ...................................................................................... 15 REVID-REVISION IDENTIFICATION REGISTER .............................................................. 16 CCODE-CALSS CODE REGISTER.................................................................................... 16 HEADT-HEAD TYPE REGISTER........................................................................................ 16 IO_RCVR-IO RECOVERY REGISTER ............................................................................... 17 WISA_STS-ISA BRIDGE ERROR STATUS REGISTER .................................................... 18
8.10 WISA_FADC-ISA BRIDGE FAST DECODERS CONTROL REGISTER ............................ 18 8.11 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL REGISTER....... 18 8.12 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL REGISTER....... 18 8.13 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 2 MASK CONTROL REGISTER....... 19 Publication Release Date: May 18, 2005 Revision A1
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W83628F & W83629D
8.14 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 3 MASK CONTROL REGISTER....... 19 8.15 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 4 MASK CONTROL REGISTER....... 19 8.16 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 5 MASK CONTROL REGISTER....... 19 8.17 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 6 MASK CONTROL REGISTER....... 19 8.18 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 7 MASK CONTROL REGISTER....... 20 8.19 WISA_FADCB0-ISA BRIDGE FAST DECODERS # 0 BASE ADDRESS REGISTER ........ 20 8.20 WISA_FADCB1-ISA BRIDGE FAST DECODERS # 1 BASE ADDRESS REGISTER ........ 20 8.21 WISA_FADCB2-ISA BRIDGE FAST DECODERS # 2 BASE ADDRESS REGISTER ........ 20 8.22 WISA_FADCB3-ISA BRIDGE FAST DECODERS # 3 BASE ADDRESS REGISTER ........ 20 8.23 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS REGISTER ........ 20 8.24 WISA_FADCB5-ISA BRIDGE FAST DECODERS # 5 BASE ADDRESS REGISTER ........ 21 8.25 WISA_FADCB6-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS REGISTER ........ 21 8.26 WISA_FADCB7-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS REGISTER ........ 21 8.27 WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1................................................ 21 8.28 WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2................................................ 22 8.29 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3................................................ 22 8.30 WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4................................................ 23 8.31 WISA_TSTREG-ISA BRIDGE TEST REGISTER................................................................ 23 9. PACKAGE DIMENSIONS 1 FOR W83628F (128-PIN PQFP) ..................................................... 24 10. PACKAGE DIMENSIONS 2 FOR W83629D (48-PIN LQFP) ....................................................... 24 11. REVISION HISTORY..................................................................................................................... 25
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W83628F & W83629D
1. GENERAL DESCRIPTION
W83628F is a PCI-to-ISA bus conversion IC. W83629D is a condensed centralizer IC for IRQ and DMA control. W83628F and W83629D together form a complete set for the PCI-to-ISA bridge. For the new generation Intel chipset Camino and Whitney, featuring LPC bus, there is no support for ISA bus and slots. However the demand of ISA devices still exist. For such case, W83628F plus W83629D are the best companion solution for the non-ISA chipset. Also the packages of W83628F (128-QFP) and W83629D (48-LQFP) had been chosen to be the most economic solution for save the M/B board layout size and cost. For the new generation chipset featuring LPC interface and support no ISA bus, W83627HF/F (Winbond LPC I/O) together with the set of W83628F and W83629D is the complete solution.
2. FEATURES
PCI to ISA Bridge
* * * * * * * * * Full ISA Bus Support including ISA Masters 5V ISA and 3.3V PCI interfaces PC/PCI DMA protocol for Software Transparent IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ Supports 3 fully ISA Compatible Slots without Buffering PCI Bus at 25MHz, 33MHz and up to 40MHz Supports Programmable ISA Bus Divide the PCI Bus Clock into 3 or 4 All ISA Signals can be Isolate Supports Configuration registers for programming performance
3. PACKAGE
* * 128-pin PQFP for W83628F 48-pin LQFP for W83629D
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
4. BLOCK DIAGRAM OF W83628F
AD[31:0] C/BE[3:0]# PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL SERR# NOGO PCIRST# PCICLK
PCI Interface ISA Interface
ISOLATE#
Signal Isolation Control
SA[19:0] SD[15:0] BALE AEN IOCHRDY IOCS16# IOCHK# IOR# IOW# LA[23:17] SBHE# MEMCS16# MEMR# MEMW# SMEMR# SMEMW# ZEROWS# MASTER# REFRESH# ROMCS# RSTDRV SYSCLK HS[2:0]
3.3V 5V
Power SuppIy
Handshaking
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W83628F & W83629D
5. BLOCK DIAGRAM OF W83629D
PCIRST# PCICLK NOGO HS[2:0]
PCI Host & Bridge Set Handshaking Logic
ISAREQ# ISAGNT#
PCI/PCI Interface
DREQ[7:5,3:0] DACK[7:5,3:0]# TC
SERIRQ
Serial to Parallel IRQ
IRQ[15,14,12:9,7:3]
3.3V 5V
Power SuppIy
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
6. PIN CONFIGURATION
6.1 PIN CONFIGURATION FOR 628F
R I E SP F R R OC RS OL I E T UAR S DCT S A AAAAG H R S E T D DDDDN # V# ## 0 1 234 D
S Y SS V S S CA CD DL 1 C6 7 K9
S A 1 8
SS AG A 1N1 7D6
S A 1 5
SS AA 11 43
N SSS A A A S S SS S VS S S S SO 1 1 1 A A AA A CA A A A AG 2 1 0 9 8 7 6 5 C4 3 2 1 0 O
11 199 9 9 99999 9 88 888888 8877 777777 7 766666 00 098 7 6 54321 0 98 765432 1098 765432 1 098765 21 0 SD5 SD4 IOCHK# ZEROWS# SD3 SD2 SD1 SD0 GND HS2 HS1 HS0 VCC IOCHRDY SMEMR# AEN SMEMW# IOR# IOW# BALE MEMCS16# IOCS16# LA17 LA18 LA19 GND 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 3VCC AD5 AD6 AD7 C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 C/BE1# GND PAR PCLK_OUT PCICLK 3VCC SERR# C/BE2# DEVSEL# TRDY# IRDY# FRAME# STOP#
W83628F
1 1 111 1 1 1 1 1 22 22 2 222 2 2 3 33 3 3 33 33 1 2 34 5 67 8 90 1 234 5 6 7 8 9 01 23 4 567 8 9 0 12 3 4 56 78
VL CA C2 0
LLL AAA 222 123
MM S S SS E E D D DD MM 8 9 1 1 01 RW ## L A 2 2
S S S S G MS A A A D D D D N A B DDD 1 1 1 1 DSH3 3 2 2 3 4 5 TE109 E# R #
A AA AA D DD DD 22222 87654
3 CI A V/ DD CBS 2 CEE 3 3L #
AA A A AAA G DD D D D DD N 2221111 D 2109876
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W83628F & W83629D
6.2 PIN CONFIGURATION FOR 629D
D R NQ C7
D A C K 7 #
D R Q 6
D A C K 6 #
D R Q 5
D D A C DA K GR C 5 NQK # D3 3
D RV QC 2C
NC NC NC NOGO ISAREQ# ISAGNT# GND PCICLK NC SERIRQ PCIRST# 3VCC
37
36
25
24
DACK2# DRQ1 DACK1# DRQ0 DACK0# TC GND HS2 HS1 HS0 VCC IRQ15
W83629D
48 1 12
13
GI NR DQ 3
I R Q 4
I R Q 5
I R Q 6
I VI I I RCR RR QD Q QQ C 7 911 01
I R Q 1 2
I R Q 1 4
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
7. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details. I/O12t I/O24t I/O12tp3 I/O24tp3 I/OD12t I/O24t OUT12t OUT24t OUT12tp3 OUT24tp3 OD12 OD24 INcs INt INtd INts INtsp3 - TTL level bi-directional pin with 12 mA source-sink capability - TTL level bi-directional pin with 24 mA source-sink capability - 3.3V TTL level bi-directional pin with 12 mA source-sink capability - 3.3V TTL level bi-directional pin with 24 mA source-sink capability - TTL level bi-directional pin open drain output with 12 mA sink capability - TTL level bi-directional pin with 24 mA source-sink capability - TTL level output pin with 12 mA source-sink capability - TTL level output pin with 24 mA source-sink capability - 3.3V TTL level output pin with 12 mA source-sink capability - 3.3V TTL level output pin with 24 mA source-sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 24 mA sink capability - CMOS level Schmitt-trigger input pin - TTL level input pin - TTL level input pin with internal pull down resistor - TTL level Schmitt-trigger input pin - 3.3V TTL level Schmitt-trigger input pin
7.1 W83628F PIN DESCRIPTION
7.1.1 PCI Interface
SYMBOL PIN I/O FUNCTION
19-26 30-37 AD[31:0] 52-59 61-63 66-70 C/BE[3:0]# 28,45 51,60
I/O24tp3 I/O24tp3
PCI Bus Address and Data Signals. The standard PCI address and data lines. Address is driven with FRAME# assertion, data is driven or received in following clocks. PCI Bus Command and Byte Enables. During the address phase of a transaction C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as Byte Enables. PCI Bus System Clock. PCICLK provides timing for all transactions on the PCI bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. PCI Bus System Clock DPLL Output. The PCLK_OUT can reduce the PCICLK Loading and it produced from internal DPLL.
PCICLK
47
INt
PCLK_OUT
48
OUT12t
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W83628F & W83629D
4.1.1 PCI Interface, contiuned
SYMBOL
PIN
I/O
I/O24tp3
FUNCTION
FRAME# IDSEL STOP# IRDY# TRDY#
40 29 39 41 42
Frame Signal. FRAME# is driven by the current PCI bus master to indicate the beginning and duration of an access. Initialization Device Select. IDSEL is used as a chip select during configuration read and write transactions. This signal should be externally tied to one of the upper 21 address signals. Bus Stop#. STOP# indicates the current target is requesting the master to stop the current PCI bus transaction. Initiator Ready. IRDY# indicates the initiating agent ability to complete the current data phase of the PCI bus transaction. Target Ready. TRDY# indicates the target agent's ability to complete the current data phase of the PCI bus transaction. Device Select. W83628F drives DEVSEL# to indicate that it is the target of the current PCI bus transaction. W83628F uses subtractive decoding and the NOGO protocol to claim PCI transactions. System Error. SERR# can be pulsed active by any PCI agent that detects a system error condition. Parity Signal. W83628F generates even parity across AD[31:0] and C/BE[3:0]#. PCI Reset. W83628F receives PCIRST# as a reset from the PCI Bus.
INt
I/O12tp3 I/O12tp3 I/O12tp3
DEVSEL#
43
I/O12tp3
SERR# PAR PCIRST#
45 49 71
OD12
I/O12tp3
INt
7.1.2 Control Logic and Handshaking Signals
SYMBOL PIN I/O FUNCTION
Handshaking Signals. HS[2:0] connected to W83629D for PCI to ISA SET handshaking signals. HS[2:0] 112114 I/O12 HS1 is handshaking Signal 1, this pin weak pulled-down during PCIRST# is asserted, and apply a pull-up resistor(4.7Kohm) to this pin disables ISA bridge subtraction decoder. Isolation Control Input. Isolate# is an active low signal by user programming to control the W83628F all output signals to Isolation and Tri-state. NOGO, This signal indicates which master initiated the current transaction and also indicates whether or not the current bus cycle is targeted for the ISA bus. This signal is a point-to-point connection between PCI HOST Bridge and W83628F.
ISOLATE#
72
INt
NOGO
76
INt
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
7.1.3 ISA Interface Signals
SYMBOL PIN I/O FUNCTION
SA[19:17]
98-96
OUT24t
System Address Bus. These are the upper address lines that define the ISA's byte granular address space (up to 1 Mbyte). SA[19:17] are at an unknown state upon PCIRST#. System Address Bus. These are the bi-directional lower address lines that define the ISA's byte granular address space (up to 1 Mbyte). SA[16:0] are at an unknown state upon PCIRST#.
SA[16:0]
94-83 81-77 110107, 104,
I/O24t
SD[15:0]
103, 101, 100, 8-15
I/O24t
System Data. SD[15:0] provide the 16-bit data path for devices residing on the ISA Bus. The W83628F tri-states SD[15:0] during PCIRST#.
AEN IOR# IOW# IOCHRDY SYSCLK RSTDRV IOCS16# SBHE# IOCHK#
118 120 121 116 99 74 124 18 105
OUT24t I/O24t I/O24t I/O24t OUT24t OUT24t INt I/O24t INt
Address Enable. AEN is asserted during DMA cycles. This signal is also driven high during W83628F initiated refresh cycles. AEN is driven low upon PCIRST#. I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive data on to the ISA data bus (SD[15:0]). I/O Write. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD[15:0]). I/O Channel Ready. Resources on the ISA Bus negate IOCHRDY to indicate that additional time (wait states) is required to complete the cycle. ISA System Clock. SYSCLK is the reference clock for the ISA bus. The SYSCLK is generated by dividing PCICLK by 3 or 4. Reset Drive. W83628F asserts RSTDRV to reset devices that reside on the ISA Bus. The W83628F asserts this signal while the PCIRST# is asserted. 16-bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles. System Byte High Enable. SBHE# asserted indicates that a byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is at an unknown state upon PCIRST#. I/O Channel Check. IOCHK# can be driven by any resource on the ISA bus during on detection of an error.
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W83628F & W83629D
4.1.3 ISA Interface Signals, contiuned
SYMBOL
PIN
I/O
FUNCTION
MEMR# MEMW# MASTER#
6 7 17 5-2 127125
I/O24t I/O24t INt I/O24t
LA[23:17]
ROMCS#
73
I/O12
REFRESH#
75
I/O24t
ZEROWS#
106
INt
SMEMR#
117
OUT24t OUT24t
SMEMW#
119
BALE
122
OUT24t
MEMCS16#
123
OD24
Memory Read. MEMR# asserted indicates the current ISA bus cycle is a memory read. Memory Write. MEMW# asserted indicates the current ISA bus cycle is a memory write. MASTER#. This signal is used with a DREQ line by an ISA master to gain control of the ISA Bus. Unlatched Address. The LA[23:17] address lines are bidirectional. These address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when the W83628F owns the ISA Bus. ROMCS# ,this pin weak pulled-down during PCIRST is asserted, and apply a pull-up resistor (4.7 Kohm) to this pin enable positive decoder of BIOS address range (depend on Configure register 70 , bit 3,2). When BIOS assress range is enabled , the PIN is BIOS ROM CS# output. Refresh. REFRESH# asserted indicates that a refresh cycle is in progress, or that an ISA master is requesting W83628F to generate a refresh cycle. Upon PCIRST#, this signal is tri-stated. Zero Wait States. An ISA slave asserts ZEROWS# after its address and command signals have been decoded to indicate that the current cycle can be executed as an ISA zero wait state cycle. ZEROWS# has no effect during 16-bit I/O cycles. Standard Memory Read. SMEMR# asserted indicates the current ISA bus cycle is a memory read cycle to an address below 1 Mbyte. Standard Memory Write. SMEMW# asserted indicates the current ISA bus cycle is a memory write cycle to an address below 1 Mbyte. Bus Address Latch Enable. BALE is an active high signal asserted by the W83628F to indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE. BALE remains asserted throughout DMA and ISA master cycles. BALE is driven low upon PCIRST#. Memory Chip Select 16. MEMCS16# asserted indicates that the memory slave supports 16-bit accesses.
7.1.4 Power Signals
SYMBOL PIN I/O FUNCTION
VCC 3VCC GND
1, 82, 102, 115 27, 46, 64 16, 38, 50, 65, 95, 111, 128
PWR PWR PWR
5V Supply. 3.3V Supply. Ground.
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
7.2 W83629D PIN DESCRIPTION
7.2.1 Control Logic and Handshaking Signals
SYMBOL PIN I/O FUNCTION
HS[2:0]
17-15
I/O12
Handshaking Signals. HS[2:0] connected to W83628F for PCI to ISA SET handshaking signals. NO GO. This signal indicates which master initiated the current transaction and also indicates whether or not the current bus cycle is targeted for the ISA bus. This signal is a point-to-point connection between PCI HOST Bridge and W83628F. PCI Bus System Clock. PCICLK provides timing for all transactions on the PCI bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. PCI Reset. W83628F receives PCIRST# as a reset from the PCI Bus.
NOGO
40
INt
PCICLK
44
INt
PCIRST#
47
INt
7.2.2 PC/PCI Interface
SYMBOL PIN I/O FUNCTION
ISAREQ#
41
OUT24t
ISA Bus Request. This signal is a point-to-point signal between W83629D and a PCI HOST arbiter . The W83629D asserts this signal according to the PC/PCI protocol. ISA Bus Grant. This signal is a point-to-point signal between W83629D and a PCI HOST Bridge's secondary bus PCPCIGNT# signal. W83629D asserts this signal according to the PC/PCI protocol. DMA Request. The DREQ signal indicates that either a slave DMA device is requesting DMA services, or an ISA bus master is requesting use of the ISA bus.
ISAGNT#
42 35,33
INt
DRQ [7:5,3:0]
31,28 26,23 21 34,32
INt
DACK [7:5,3:0]# TC
30,27 24,22 20 19
OUT24t
DMA Acknowledge. The DACK# signal indicates that either a DMA channel or an ISA bus master has been granted the ISA bus. Terminal Count. The W83628F asserts TC to DMA slaves as a terminal count indicator.
OUT24t
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W83628F & W83629D
7.2.3 IRQ Serializer Interface
SYMBOL PIN I/O FUNCTION
SERIRQ IRQ [3:7,9:12,14,15]
46 2-6 8-13
I/OD12t
Serial Interrupt Requested Signals. This signal is for transfer IRQ mode between parallel IRQ to serial IRQ. Parallel Interrupt Requested Input.
INt
7.2.4 Power Signals
SYMBOL PIN I/O FUNCTION
VCC 3VCC GND 7.2.5 NC Pins
SYMBOL
7, 14, 25 48 1, 18, 29, 43
PWR PWR PWR
5V Supply. 3.3V Supply. Ground.
PIN
I/O
FUNCTION
NC
36, 37,38, 39, 45
No Connection.
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
8. PCI CONFIGURATION REGISTERS
8.1 VID-VENDOR IDENTIFICATION REGISTER
Address Offset: Default Value: Attribute: 00-01h 1050h Read only
This register is read-only and contains Winbond vendor identification number(1050h).
8.2 DID-DEVICE IDENTIFICATION REGISTER
Address Offset: Default Value: Attribute: 02-03h 0628h Read only
This register is read-only and contains the device identification number(0628h).
8.3 PCICMD-PCI COMMAND REGISTER
Address Offset: Default Value: Attribute: 04-05h 0007h Read/Write
This register provides control over ISA bridge to generate and response to PCI cycles properly. When a 0 is written to this register, ISA bridge is to be disconnected from PCI bus for all accesses except configuration accesses. Bit 15:10 Bit 9 Bit 8 Reserved. Fast Back to Back. This bit always returns a zero. SERR# Enable. =1 =0 Bit 7 Bit 6 Bit 5 Bit 4 Enable. Disable.
Wait Cycle Control(Not supported). Hardwired to zero. Parity Error Response(Not supported). Hardwired to zero. VGA Palette Snoop Enable(Not supported). Hardwired to zero. Memory Write and Invalidate Enable(Not supported). Hardwired to zero.
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W83628F & W83629D
Bit 3 Bit 2 Parity Error Response(Not supported). Hardwired to zero. Bus Master Enable. Hardwired to one. The ISA bridge Bus Masters are always supported to generate a PCI Bus master cycle. Bit 1 Bit 0 Memory Space Enable. Hardwired to one. The ISA bridge Memory space is always enabled. I/O Space Enable. Hardwired to one. The ISA bridge I/O space is always enabled.
8.4 PCISTS-PCI STATUS REGISTER
Address Offset: Default Value: Attribute: 06-07h 0200h Read/Write
This register shows status information for PCI bus related events. Bit 15 Bit 14 Bit 13 Detected Parity Error. Hardwired to zero. The ISA bridge does not check bus parity. Signaled System Error. This bit is set when ISA bridge asserts SERR# on PCI bus. Received Master Abort Status. This bit is set when the ISA bridge is target aborted as a master on the PCI bus. Software sets this bit to 0 by writing a 1 to it. Bit 12 Received Target Abort Status. This bit is set when the ISA bridge target aborts a PCI transaction as a target. Software sets this bit to 0 by writing a 1 to it. Bit 11 Signaled Target Abort Status. This bit is set when the ISA bridge signals a target abort for a PCI transaction. Software sets this bit to 0 by writing a 1 to it. Bit 10:9 Bit 8 Bit 7 DEVSEL# Timing. This 2 bits always return a 01b(medium decode). Data Parity Detected(Not supported). Hardwired to zero. Fast Back-to-Back(Not supported). Hardwired to zero.
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
Bit 6 Bit 5 Bit 4:0 66 MHz/ 33 MHz(Only support 33 MHz). Hardwired to zero. User Defineable Features(Not supported). Hardwired to zero. Reserved. Reserved and will returns zero when reading this register.
8.5 REVID-REVISION IDENTIFICATION REGISTER
Address Offset: Default Value: Attribute: Bit 7:0 08h See lastest stepping information Read Only Revision Identification Number.
This register shows status information for PCI bus related events.
8.6 CCODE-CALSS CODE REGISTER
Address Offset: Default Value: Attribute: Bit 23:16 Bit 15:8 Bit 7:0 09-0Bh 060100h Read Only Base Class Code. 06h = Bus Bridge Sub-Class Code. 01h = PCI to ISA Bridge Programming Interface. 00h
The class code register is a read-only register and used to identify the ISA bridge.
8.7 HEADT-HEAD TYPE REGISTER
Address Offset: Default Value: Attribute: 0Eh 00h Read Only
The register is a read-only register and used to indicate that the ISA bridge configuration space adheres to PCI local bus specification. It also indicates that ISA bridge is not a multifunction device. Bit 7 Bit 6:0 Multifunction Indicator. 0 = Not a multifunction device. Layout Code. 00h = PCI layout type.
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W83628F & W83629D
8.8 IO_RCVR-IO RECOVERY REGISTER
Address Offset: Default Value: Attribute: Bit 7 40h 4Dh Read/Write SYSCLK Divider. 0 = SYSCLK is equal to PCICLK divided by 4. 1 = SYSCLK is equal to PCICLK divided by 3. Bit 6 8-bit I/O Recovery Enable 0 = Disable bits 5:3 setting and uses 3.5 SYSCLKs for 8 bit I/O recovery time. 1 = Enable bits 5:3 setting. Bit 5:3 8-bit I/O RecoveryTimes. When bit 6=1 ,this 3-bit field defines the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 8 bit I/O 000 =0 SYSCLK 001 =1 SYSCLK 010 =2 SYSCLKs 011 =3 SYSCLKs 100 =4 SYSCLKs 101 =5 SYSCLKs 110 =6 SYSCLKs 111 = 7 SYSCLKs Bit 2 16-bit I/O Recovery Enable. = 0 Ignore bits 1:0 setting and uses 3.5 SYSCLKs for 16-bit I/O recovery time. = 1 The 16-bit I/O recovery time is decided by bits 1:0. Bit 1:0 16-bit I/O Recovery Times. When bit 2=1 ,this 2-bit field defines the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 16 bit I/O = 01 = 10 = 11 = 00 1 SYSCLK 2 SYSCLKs 3 SYSCLKs 4 SYSCLKs
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
8.9 WISA_STS-ISA BRIDGE ERROR STATUS REGISTER
Address Offset: Default Value: Attribute: Bit 7:3 Bit 2 Bit 1 Bit 0 42h 00h Read/Write Reserved. IOCHK# Pin State. This bit reflects the inverse state of IOCHK# pin on the ISA bus. Reserved. Byte Lane Error. This bit is set if the ISA bridge detects an illegal byte lane combination for a PCI I/O cycles.
8.10 WISA_FADC-ISA BRIDGE FAST DECODERS CONTROL REGISTER
Address Offset: 50h Default Value: 00h Attribute: Read/Write Bit 7 Enable/Disable Fast I/O Address Decoder # 7. Bit 6 Enable/Disable Fast I/O Address Decoder # 6. Bit 5 Enable/Disable Fast I/O Address Decoder # 5. Bit 4 Enable/Disable Fast I/O Address Decoder # 4. Bit 3 Enable/Disable Fast I/O Address Decoder # 3. Bit 2 Enable/Disable Fast I/O Address Decoder # 2. Bit 1 Enable/Disable Fast I/O Address Decoder # 1. Bit 0 Enable/Disable Fast I/O Address Decoder # 0.
8.11 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL REGISTER
Address Offset: 58h Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 0, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 0.
8.12 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL REGISTER
Address Offset: 59h Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 1, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 1. -18-
W83628F & W83629D
8.13 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 2 MASK CONTROL REGISTER
Address Offset: 5Ah Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 2, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 2.
8.14 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 3 MASK CONTROL REGISTER
Address Offset: 5Bh Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 3, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 3.
8.15 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 4 MASK CONTROL REGISTER
Address Offset: 5Ch Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 4, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 4.
8.16 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 5 MASK CONTROL REGISTER
Address Offset: 5Dh Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 5, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 5.
8.17 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 6 MASK CONTROL REGISTER
Address Offset: 5Eh Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 6, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 6.
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Publication Release Date: May 18, 2005 Revision A1
W83628F & W83629D
8.18 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 7 MASK CONTROL REGISTER
Address Offset: 5Fh Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 7, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address decoder # 7.
8.19 WISA_FADCB0-ISA BRIDGE FAST DECODERS # 0 BASE ADDRESS REGISTER
Address Offset: 60-61h** Default Value: 0000h Attribute: Read/Write This register contains the base address for fast address decoder # 0.A **Note: 60h is lower byte and 61h is upper byte.
8.20 WISA_FADCB1-ISA BRIDGE FAST DECODERS # 1 BASE ADDRESS REGISTER
Address Offset: 62-63h Default Value: 0000h Attribute: Read/Write This register contains the base address for fast address decoder # 1.
8.21 WISA_FADCB2-ISA BRIDGE FAST DECODERS # 2 BASE ADDRESS REGISTER
Address Offset: 64-65h Default Value: 0000h Attribute: Read/Write This register contains the base address for fast address decoder # 2.
8.22 WISA_FADCB3-ISA BRIDGE FAST DECODERS # 3 BASE ADDRESS REGISTER
Address Offset: 66-67h Default Value: 0000h Attribute: Read/Write This register contains the base address for fast address decoder # 3.
8.23 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS REGISTER
Address Offset: 68-69h Default Value: 0000h Attribute: Read/Write This register contains the base address for fast address decoder # 4.
-20-
W83628F & W83629D
8.24 WISA_FADCB5-ISA BRIDGE FAST DECODERS # 5 BASE ADDRESS REGISTER
Address Offset: Default Value: Attribute: 6A-6Bh 0000h Read/Write
This register contains the base address for fast address decoder # 5.
8.25 WISA_FADCB6-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS REGISTER
Address Offset: Default Value: Attribute: 6C-6Dh 0000h Read/Write
This register contains the base address for fast address decoder # 6.
8.26 WISA_FADCB7-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS REGISTER
Address Offset: Default Value: Attribute: 6E-6Fh 0000h Read/Write
This register contains the base address for fast address decoder # 0.
8.27 WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1
Address Offset: Default Value: Attribute: Power-on setting bits Bit 7-6 Bit 5-4 Reserved. = 00 Send AD Bus with no STEP = 01 Send AD Bus with 2 STEP = 10 Send AD Bus with 4 STEP = 11 Reverse Bit 3-2 = 00 1MB BIOS ROM positive decode. = 01 2MB BIOS ROM positive decode. = 10 4MB BIOS ROM positive decode. = 11 8MB BIOS ROM positive decode. Bit 1 =0 Disable High-Address BIOS ROM decoder. =1 Enable High-Address BIOS ROM decoder. This bit can be set/reset by ROMCS# power-on setting during PCIRST# assert. Bit 0 =0 Normal mode. =1 Disable ISA Bridge subtraction decoder. This bit can be set/reset by HS1 power-on setting during PCIRST# assert. Publication Release Date: May 18, 2005 Revision A1 70h 000001ssb Read/Write bit 1:0 are power-on set by ROMCS# and HS1.
- 21 -
W83628F & W83629D
8.28 WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2
Address Offset: Default Value: Attribute: Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 71h 00h Read/Write =0 Enable IRQ11. =1 Disable IRQ11. =0 Enable IRQ10. =1 Disable IRQ10. =0 Enable IRQ9. =1 Disable IRQ9. =0 Enable IRQ7. =1 Disable IRQ7. =0 Enable IRQ6. =1 Disable IRQ6. =0 Enable IRQ5. =1 Disable IRQ5. =0 Enable IRQ4. =1 Disable IRQ4. =0 Enable IRQ3. =1 Disable IRQ3.
8.29 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3
Address Offset: Default Value: Attribute: Bit 7-3 Bit 2 Bit 1 Bit 0 72h 00h Read/Write Reserved. =0 Enable IRQ15. =1 Disable IRQ15. =0 Enable IRQ14. =1 Disable IRQ14. =0 Enable IRQ12. =1 Disable IRQ12.
-22-
W83628F & W83629D
8.30 WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4
Address Offset: Default Value: Attribute: Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 73h 00h Read/Write =0 Enable DRQ 7. =1 Disable DRQ 7. =0 Enable DRQ6. =1 Disable DRQ6. =0 Enable DRQ5. =1 Disable DRQ5. Reserved. =0 Enable DRQ 3. =1 Disable DRQ 3. =0 Enable DRQ 2. =1 Disable DRQ 2. =0 Enable DRQ 1. =1 Disable DRQ 1. =0 Enable DRQ 0. =1 Disable DRQ 0.
8.31 WISA_TSTREG-ISA BRIDGE TEST REGISTER
Address Offset: Default Value: Attribute: Bit 7-5 Bit 4 80h 04h Read/Write Reserved and should not write data to this register. =0 80h port decoding on subtrastive cycles of LPC I/F. =1 80h port decoding on positive cycles of LPC I/F. This Bit must be set 1when LPC I/F is only decoding on positive cycles,but when the bridge is used in PIIX4 for test set the bit to 0 . Bit 3 Bit 2-0 000 001 010 011 100 101 110 111 Reserved and should not write data to this register. - 0.8 nS. - 0.6 nS. - 0.4 nS. - 0.2 nS. 0 nS. +0.2 nS. +0.4 nS. +0.6 nS. Publication Release Date: May 18, 2005 Revision A1 For Winbond Internal Reference only.
- 23 -
W83628F & W83629D
9. PACKAGE DIMENSIONS 1 FOR W83628F (128-PIN PQFP)
HE E
102 65
Symbol
Dimension in mm
Dimension in inch
Min
0.25 2.57 0.10 0.10 13.90 19.90
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783
Nom
0.014 0.107 0.008 0.006 0.551 0.787 0.020
Max
0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 See Detail F Seating Plane A1 L L1 Detail F
y
5. PCB layout please use the "mm".
10. PACKAGE DIMENSIONS 2 FOR W83629D (48-PIN LQFP)
HD D
36 25
Symbol
Dimension in inch Min. Nom. Max.
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2 A1 y
A
Seating Plane
See Detail F
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
-24-
W83628F & W83629D
11. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
1998.11.16 1998.11.19
Add High-Address BIOS ROM decoder function(CS#/HS3). (Page 7 & Page 20) Change decode range to #FFF00000~#FFFFFFFF & #000E0000~#000FFFFF. Supports 3 fully ISA Compatible Slots without Buffering. Rename HS3. it is renamed to ROMCS# in W83628F,and NC in W83629D. Indicate the Bit 4 of offset address 80h is used to enable 80h port decoding when only positive decoding switched of LPC I/F. 25 ADD Important Notice
1999.01.17
0.32 A1
1999.04.21 May 18, 2005
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 25 -
Publication Release Date: May 18, 2005 Revision A1

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